1. Field of the Invention
The present invention relates generally to data communication networks and, more specifically, to a method and system for testing the bit lock performance of a clock and data recovery circuit.
2. Discussion of Related Art
Timing jitter is an important parameter in characterizing the performance of digital systems. In a digital system, timing jitter represents the difference between the time an edge event occurs and the ideal edge time of the event. The presence of timing jitter in a reference clock signal often translates directly into output data jitter within digital transceiver systems. Accordingly, as new designs implement increasing data transfer speeds, precise timing accuracy proves critical to the link performance of digital transceiver systems.
Timing jitter in a digital system may include random jitter (“RJ”) and deterministic jitter (“DJ”). RJ is a component of timing jitter that is unbounded in amplitude and typically modeled by a Gaussian probability distribution. Thermal noise within the electrical circuit is often the primary cause of RJ. DJ is a component of timing jitter that is bounded in amplitude and predictable in nature. DJ may comprise multiple types of timing jitter, including data-dependent jitter (“DDJ”), sinusoidal jitter (“SJ”), and data-uncorrelated jitter (“DUJ”). DDJ comprises any DJ that correlates with data edge transitions, and often occurs when data edge transitions are distorted by limited data path bandwidth. SJ is periodic in nature and can be attributed to signal crosstalk. Finally, DUJ corresponds to DJ which does not correlate with data edge transitions.
The presence of timing jitter in a digital system is detrimental to overall system performance. Specifically, timing jitter may result in a reduction of digital signal eye openings and an increase of the overall bit error ratio (“BER”) of the transceiver system due to narrowing of the signal's effective sampling window. FIG. 1 illustrates the relationship between timing jitter and BER in a serial transceiver link 100. Two ideal digital pulses 104 without data jitter are shown centered one unit interval (“UI”) 108 apart. A distribution function 102 is shown illustrating the probability distribution of digital pulses having timing jitter. Increased timing jitter corresponds with increased data signal eye closure 106, 112 and a reduction in the overall eye opening 110. As increased eye closure reduces the effective sampling window of the data signal, it becomes crucial to perform careful analysis of a high-speed serial transceiver system's response to timing jitter, especially with respect to the transceiver's clock and data recovery (“CDR”) circuit.
Therefore, in light of the foregoing description, it is desirable to provide a method and system for efficient and accurate testing and characterization of a CDR system's ability to operate in the presence of jitter.